Arm

The ARM Cortex-M0 processor implements the PendSV exception handler to allow low priority interrupts to preempt current execution. However, the use of a bootloader can impact how PendSV exceptions are handled. This article provides an in-depth look at PendSV exception handling on the Cortex-M0 and examines how a bootloader can affect it. Overview of PendSV…

The Cortex-M0 processor implements a basic exception model with 7 exception types. The PendSV (pendable service request) exception is one of these and allows low priority or background tasks to be run when no other exception is active. Handling the PendSV exception properly is key to implementing an RTOS or multitasking firmware on Cortex-M0 devices….

When developing embedded systems using the ARM Cortex-M0 processor and a bootloader, you may encounter issues with incorrect vector tables causing the system to crash or behave erratically on startup. The root cause is often a mismatch between the vector table defined in the bootloader code and the application code. This article provides a guide…

The Cortex-M0 and Cortex-M3 are two popular ARM processor cores used in many embedded and IoT applications. Both support vector table remapping, which allows flexibility in locating the exception/interrupt vector table. However, there are some key differences between the Cortex-M0 and Cortex-M3 implementations of vector table remapping that developers need to be aware of. Overview…

When a context switch occurs on a Cortex-M0 processor, the state of the current thread must be saved so that it can be restored when the thread is switched back in. This includes saving the values of all registers that are modified by the thread. The processor must also load the register values for the…

The Cortex-M0 is one of ARM’s smallest and simplest microcontroller cores, aimed at low-cost and low-power embedded applications. Like all Cortex-M cores, the M0 starts execution at the reset vector located at address 0x00000000. This reset vector points to the initial stack pointer value and the reset handler function. The vector table on Cortex-M0 contains…

Context switching on Cortex-M0 microcontrollers can impact real-time performance if not optimized properly. By following best practices like minimizing the number of context switches, reducing switch latency, and tuning interrupt handling, significant improvements are possible. Understanding Context Switching A context switch occurs when the processor stops what it is currently doing, saves its state to…

When developing embedded systems using ARM Cortex-M processors, a common issue that can occur is the bootloader causing an incorrect vector table and problems with the PendSV interrupt. This can lead to hard-to-diagnose faults and system crashes. In this article, we’ll examine the root causes of this issue and provide solutions to resolve it. The…

Context switching on Cortex-M0 microcontrollers can be problematic due to the limited resources available on these low-cost ARM chips. While context switching is possible on Cortex-M0, it requires careful planning and programming to avoid issues. This article examines the challenges of context switching on Cortex-M0 and provides recommendations for successfully implementing preemptive multitasking. The Problem…

The Cortex-M0 and Cortex-M1 are two of ARM’s most widely used cores for microcontroller applications. With their low power consumption, small silicon footprint, and optimized Thumb-2 instruction set, they are ideal for cost-sensitive and power-constrained embedded systems. However, writing efficient code for these cores requires an understanding of their architecture and the toolchain used to…