Arm

ARM processors power billions of devices around the world. From smartphones to smartwatches, ARM chips provide the processing power for many of our everyday gadgets. Understanding the ARM Cortex numbering scheme is key to identifying capabilities and features of ARM-based systems. ARM Cortex series processors are grouped into three main families – Cortex-A, Cortex-R, and…

The short answer is yes, ARM does assume that all Cortex-M microcontrollers are little-endian by default. However, Cortex-M CPUs do have configuration options to enable big-endian data accesses if required by the system design. Introduction to Endianness Endianness refers to the byte ordering used to represent data in memory and during data transfers. There are…

Overview of Instruction Fetch in Cortex M The IFU fetches instructions from memory and feeds them to the execution pipeline. It contains a prefetch buffer that caches instructions. The prefetch buffer helps reduce stalls when fetching from slower memories. The IFU also handles branching by fetching instructions from the new branch target address. In Cortex…

The short answer is yes, the NonMaskable Interrupt (NMI) on ARM Cortex M processors is non-clearable by software. The NMI is designed to be triggered by hardware events that require immediate attention from the processor, even during critical operations. Unlike regular interrupts, NMIs cannot be disabled or masked at any time. Once asserted, the NMI…

A usage fault exception in ARM Cortex M processors indicates an invalid memory access or illegal attempt to execute an instruction. It occurs when the processor tries to access restricted memory regions, executes an undefined instruction, uses a coprocessor instruction when no coprocessor is present, accesses a disabled memory region, or performs an unaligned memory…

Handling interrupts efficiently is key for responsive real-time embedded systems. For C++ projects on ARM Cortex-M devices, it can be very useful to directly call C++ object member functions from the interrupt handler. This allows object-oriented encapsulation of interrupt handling logic while still providing low latency and quick response to events. With proper configuration, member…

NULL pointer dereferences are a common source of bugs and security vulnerabilities in embedded systems built on ARM Cortex-M CPUs. Enabling the Memory Protection Unit (MPU) on Cortex-M3 and above devices provides an effective mitigation by preventing access to address 0x00000000, the NULL pointer address. This article explains how to configure the MPU regions to…

When developing for ARM Cortex-M microcontrollers, the choice of compiler toolchain is an important decision that can significantly impact development time, code performance, and cost. The main compiler options for Cortex-M development include Keil MDK, IAR Embedded Workbench, GNU toolchains like GNU Arm Embedded Toolchain or Arm Embedded GCC, Yagarto, and Linaro. Here is an…

The Cortex-M3 processor from ARM is designed to be an extremely low power 32-bit microcontroller. Its power efficiency comes from multiple architectural design choices that aim to reduce power consumption during both active operation and idle periods. Power Saving Modes The Cortex-M3 has several low power modes that allow peripherals and CPU functionality to be…

The ARM Cortex M3 processor is a 32-bit microcontroller CPU core designed for embedded applications requiring high performance and low power consumption. Some key features of the Cortex M3 include its Thumb-2 instruction set architecture, 3-stage pipeline, Memory Protection Unit, and low power sleep modes. Introduction to ARM Cortex M3 ARM Holdings introduced the Cortex…