Arm

The Arm architecture includes two important branch and link instructions – BL and BLX. These instructions allow you to branch or jump to a different part of your program, while also storing the return address so you can later return back to where you came from. In this article, we will demystify these instructions and…

The ARM Cortex-M3 is a 32-bit processor core licensed by ARM Holdings. It includes specific instruction sets for enhanced real-time performance, system control and monitoring, security, and power efficiency. One key set of instructions are the branch instructions, which allow the processor to conditionally change the control flow of a program. In simple terms, branch…

Interrupts are a critical part of embedded systems, allowing time-critical tasks to be executed with minimal latency. However, there can be significant differences in interrupt latency depending on the type of interrupt and how it is configured. This article examines the latency differences between three common types of interrupts on ARM Cortex chips: timer interrupts,…

The key to measuring interrupt latency is utilizing the ARM Cortex chip’s timers and GPIO pins. By configuring a timer to trigger a GPIO interrupt at precise intervals, we can measure the time elapsed between the timer interrupt request and the execution of the GPIO interrupt handler. This provides an accurate measurement of the interrupt…

Interrupt latency refers to the time it takes for an interrupt request to be serviced after it is asserted. There are various factors that can influence interrupt latency in an ARM Cortex system. The key factors include: Interrupt Controller Design The interrupt controller plays a critical role in determining interrupt latency. Factors like the number…

Interrupt latency is an important performance metric for real-time embedded systems built around Arm Cortex-M processors. It refers to the time elapsed from when an interrupt is generated to when the first instruction of the interrupt handler starts executing. Minimizing interrupt latency allows real-time tasks and events to be handled more responsively. This article provides…

The vector table in Cortex-M3 microcontrollers contains the reset value and exceptions handler addresses. Its placement in memory is an important consideration during application development. This article provides a detailed overview of vector table placement options and considerations for Cortex-M3 devices. Introduction to Vector Table The vector table contains the initial stack pointer value and…

The ARM processor has several different processor modes that allow access to different resources and functionality. The current processor mode is stored in the Current Program Status Register (CPSR). By writing values to specific bits in the CPSR, the processor mode can be changed. This allows switching between modes like User mode, FIQ mode, IRQ…

The ARM CPSR (Current Program Status Register) controls the processor operating mode and enables switching between different modes in ARM cores. The CPSR stores status and control information such as the ALU flags, current processor mode, and interrupts enabling/disabling. Changing the mode field in the CPSR allows switching between different processor modes. ARM Processor Modes…

The Application Program Status Register (APSR) is one of the key registers in the ARM Cortex series of processors. It contains important status and control information related to the execution state of an application program. Directly accessing the APSR can provide valuable insights into the current state of the processor and allow modifying certain control…