Arm

ARM Cortex-M processors can be configured with either a unified or separate memory address space for code and data. The choice impacts performance, software design, and memory protection capabilities. Unified Memory Address Space In the unified memory address space configuration, both code and data share the same logical address space. All memory access instructions like…

The ARM Cortex-M series of microcontroller chips utilize a modified Harvard architecture. This architecture separates instruction and data memories into distinct address spaces, while still allowing tight coupling between the two for flexibility. The separation provides several advantages in embedded systems such as deterministic instruction fetch, higher performance, and simpler memory subsystem design. Overview of…

The key difference between Harvard and Von Neumann architectures is that Harvard architecture has physically separate storage and signal pathways for instructions and data, while Von Neumann architecture uses the same memory and pathways for both instructions and data. This separation allows Harvard architecture to achieve greater parallelism and throughput for certain workloads. What is…

Bit-banding is a feature in some Arm Cortex processors that allows single bit modifications to be made to memory mapped peripherals without the overhead of a read-modify-write sequence. This provides an efficient mechanism to set or clear individual bits in registers. Bit-band regions map a complete word in memory to a single bit in the…

The ARM architecture supports both conditional and unconditional branches to alter the flow of program execution. Conditional branches test a condition code and branch if the condition is true, while unconditional branches always branch. The processor mode determines which instructions are available and what privileges the code has access to. This article will explore conditional…

When writing assembly code for ARM Cortex chips using Thumb instruction set, the BX and BLX instructions allow you to switch between Arm and Thumb states. Using them correctly is crucial for ensuring proper program execution flow. This comprehensive guide will provide developers with a deep understanding of how to utilize BX and BLX properly…

When programming for the Cortex-M3 processor, it is important to keep the processor in Thumb mode rather than ARM mode. Thumb mode uses 16-bit Thumb instructions which take up less memory space than 32-bit ARM instructions. Staying in Thumb mode ensures your code remains compact and efficient. Here are some techniques to keep the Cortex-M3…

The Cortex-M3 processor implements the ARM Thumb-2 instruction set architecture, which includes 16-bit and 32-bit instructions. The 16-bit instruction set provides a rotate right (ROR) instruction but not a rotate left (ROL) instruction. The 32-bit instruction set does include both ROR and ROL instructions. The main reason the 16-bit Thumb instruction set only has ROR…

The ARM Cortex series of chips support conditional execution of instructions using the Compare and Branch instructions CBZ and CBNZ. These allow you to efficiently compare a register against zero and conditionally branch based on the result. This provides a way to implement conditional logic and flow control without having to explicitly compare and branch,…

Indirect branching allows jumping to an address stored in a register, providing flexibility in control flow. The Arm instruction set includes two main indirect branch instructions – BX and BLX. This article will explain how they work and when to use each one. What is an Indirect Branch? An indirect branch occurs when the destination…