RME-DA Support for On-Chip Devices and PCIe Integration
The Realm Management Extension (RME) is a critical component of ARM’s security architecture, designed to provide hardware-enforced isolation between different software domains. RME-DA (Device Attribution) is a feature within RME that manages device access to memory, ensuring that devices can only access memory regions they are explicitly permitted to. A common point of confusion arises when determining whether RME-DA supports on-chip devices, particularly those connected via AXI buses, as opposed to PCIe devices. This issue is further complicated by the lack of clarity in defining what constitutes an "on-chip device" and how RME-DA interacts with different types of devices.
The core of the issue lies in the distinction between devices connected via PCIe and those connected via AXI. PCIe devices are typically external peripherals, such as GPUs or network cards, while AXI-connected devices are often on-chip components like GPUs, memory controllers, or other peripherals integrated into the System-on-Chip (SoC). The confusion stems from the fact that RME-DA is often associated with PCIe devices, leading to the assumption that it does not support AXI-connected on-chip devices. However, this is not entirely accurate. RME-DA can support on-chip devices, but the mechanism of support differs based on the bus architecture and the device’s integration into the system.
Memory Coherency and Bus Architecture in RME-DA
The primary factor determining RME-DA support for a device is not whether the device is on-chip or off-chip, but rather the bus architecture through which the device is connected to the system. PCIe devices are inherently non-coherent, meaning they do not automatically synchronize their memory accesses with the CPU’s cache. This non-coherency necessitates explicit management of memory access permissions, which is where RME-DA comes into play. RME-DA ensures that PCIe devices can only access memory regions that have been explicitly allocated to them, preventing unauthorized access to sensitive data.
On the other hand, AXI-connected devices are typically coherent, meaning their memory accesses are automatically synchronized with the CPU’s cache. This coherency is managed by the system’s cache coherency protocol, which ensures that all devices see a consistent view of memory. However, this does not mean that RME-DA cannot support AXI-connected devices. The key difference is that RME-DA’s role in managing AXI-connected devices is less about enforcing memory access permissions and more about integrating these devices into the broader security framework provided by RME.
The distinction between PCIe and AXI-connected devices becomes particularly important when considering devices like GPUs, which can be connected via either bus. For example, an on-chip Mali GPU connected via AXI would be considered an on-chip device, while an external NVIDIA GPU connected via PCIe would be classified as an off-chip device. In both cases, RME-DA can provide support, but the implementation details differ based on the bus architecture.
Implementing RME-DA for On-Chip Devices and PCIe Integration
To effectively implement RME-DA for on-chip devices and PCIe integration, several steps must be taken to ensure proper configuration and operation. The first step is to identify the bus architecture through which the device is connected. For PCIe devices, this involves configuring the Root Complex Integrated Endpoint (RCiEP) to support RME-DA. The RCiEP is responsible for translating PCIe transactions into the system’s memory space, and it must be configured to enforce the memory access permissions defined by RME-DA.
For AXI-connected devices, the implementation of RME-DA is more closely tied to the system’s cache coherency protocol. Since AXI-connected devices are typically coherent, RME-DA’s role is to ensure that these devices are properly integrated into the security framework. This may involve configuring the device’s memory access permissions at the system level, ensuring that the device can only access memory regions that have been explicitly allocated to it.
In addition to configuring the bus architecture, it is also important to consider the specific requirements of the device itself. For example, a GPU may require additional configuration to ensure that its memory accesses are properly synchronized with the CPU’s cache. This may involve configuring the GPU’s memory management unit (MMU) to enforce the memory access permissions defined by RME-DA.
Finally, it is important to consider the broader system architecture when implementing RME-DA. This includes ensuring that the system’s memory map is properly configured to support the memory access permissions defined by RME-DA, as well as ensuring that the system’s cache coherency protocol is properly configured to support the devices connected to the system.
In summary, RME-DA can support both on-chip and off-chip devices, but the implementation details differ based on the bus architecture and the device’s integration into the system. By properly configuring the bus architecture, the device’s memory access permissions, and the broader system architecture, it is possible to effectively implement RME-DA for both on-chip devices and PCIe integration.
