Utilizing Dual Stack Pointers (MSP and PSP) Without an RTOS

ARM Cortex-M processors provide two stack pointers, the main stack pointer (MSP) and process stack pointer (PSP), that enable dual-stacked operation without requiring an RTOS. This allows developers working on bare-metal embedded projects to take advantage of the flexibility and power of dual stacking while avoiding the complexity and overhead of an RTOS. Introduction to…

Determining Stack Requirements When Using an RTOS on Arm Cortex-M

When developing embedded systems using an RTOS (real-time operating system) on an Arm Cortex-M processor, properly determining the stack requirements for each task is crucial for avoiding stack overflows and system crashes. The key factors that influence stack usage are the RTOS itself, the Cortex-M core, and the application code. By analyzing these elements, stack…

Calculating Maximum Stack Usage for Bare Metal Arm Cortex-M Apps

When developing bare metal applications for Arm Cortex-M microcontrollers, determining the maximum stack usage is crucial for allocating sufficient stack memory and avoiding stack overflows. This article provides a detailed guide on techniques and tools for accurately measuring stack usage in bare metal Cortex-M apps. Introduction to Stack Usage in Cortex-M Apps In Cortex-M microcontrollers,…

Stack Usage Reporting in Arm Development Tools

Understanding and optimizing stack usage is an important part of developing efficient software for Arm-based systems. The stack is a region of memory used to store temporary variables created by functions and invoked during program execution. Keeping stack usage low improves performance and helps prevent stack overflows that can cause crashes or undefined behavior. Arm’s…

Estimating Stack Memory Needs for Arm Cortex-M Applications

When developing applications for Arm Cortex-M based microcontrollers, properly estimating the stack memory requirements is crucial for optimizing memory usage and avoiding stack overflows. This article provides a comprehensive guide on techniques and best practices for calculating your Cortex-M application’s stack needs. What is the Stack? The stack is a region of memory used to…

Debugging Cortex-M1 DesignStart Projects with DAPLink

The Cortex-M1 processor from ARM is a popular choice for IoT and embedded devices. DesignStart is a free IP platform from ARM that allows developers to easily integrate Cortex-M1 into their custom SoC designs. While DesignStart simplifies integration, debugging these custom designs brings unique challenges. This article provides a guide to debugging DesignStart Cortex-M1 projects…

Execution Latency of ITCM vs External RAM on Cortex-M1

The Cortex-M1 processor has an internal tightly coupled memory (ITCM) that allows for lower latency access compared to external RAM. When executing code and data from ITCM, the Cortex-M1 can achieve single-cycle access. However, when accessing external RAM, it experiences higher latency due to factors like bus contention, wait states, and caching. ITCM Overview The…